Design of Shift Register with Minimized Area by Using 4 Bit Hybrid Latch

Abstract

SHIFT REGISTERS has been used as a gateway for designing very high-speed VLSI circuits. It is designed using the efficient pulsed latch technique. Efficient pulsed latch is replacement of flip-flops with hybrid latch. It has single phase clock and triggering on one edge. This paper proposes hybrid latch flip flop design to redu ce power consumption with use of smaller flip flops thus the area will be minimized. Shift register has been designed in 16nm CMOS technology.