A Framework for Semiconductor Faults Detection and Classification in Wafer Fabrication Processes: Improving Yield and Quality Control

Abstract

This thesis presents a framework for semiconductor faults detection and classification (FDC) in wafer fabrication processes. The goal is to detect abnormal events and reduce abnormal yield loss by monitoring and analyzing wafer fabrication profile data from a large number of related process variables. The emphasis is on managing ingot fabrication and improving ingot quality, which is the first material manufactured for wafers. Quality parameters are used to evaluate the ingot quality, and statistical methods are applied for data generation. The suggested framework employs a regulated limit and simple rules to detect aberrant wafers and aid in the detection of semiconductor problems for process recovery. The results demonstrate the practical applicability of the proposed approach in improving yield and quality control in semiconductor manufacturing processes. The findings contribute to the field of semiconductor manufacturing and can be applied to other manufacturing processes as well.