GAYATHRI T; KALAISELVY S. Design of Shift Register with Minimized Area by Using 4 Bit Hybrid Latch. International Journal of Progressive Research in Science and Engineering , [S. l.], v. 1, n. 5, p. 140–142, 2020. Disponível em: https://journal.ijprse.com/index.php/ijprse/article/view/171. Acesso em: 22 jul. 2024.